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All edits made to a page by one user, in chronological order.
| Page | Talk:Sunway TaihuLight (Log · Page History) |
| User | The Anome (Edit Counter· Top Edits) |
| Total edits | 18 |
| Minor edits | 0 (0%) |
| (Semi-)automated edits | 0 (0%) |
| Reverted edits | 0 (0%) |
| atbe1 | 0.5 |
| Added (bytes)2 | 3,504 |
| Deleted (bytes) | 0 |
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0 (0%)
Major edits
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18 (100%)
(Semi-)automated edits
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0 (0%)
Manual edits
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18 (100%)
Reverted edits
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0 (0%)
Unreverted edits
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18 (100%)
1 Average time between edits (days)
2 Added text is any positive addition that wasn't reverted (approximate)
| Date | Links | Size | Edit summary |
|---|---|---|---|
| 2016-06-29 11:17 | Diff · History | 323 | →"Sunway" vs. "ShenWei": In particular, [http://engine.scichina.com/publisher/scp/journal/SCIS/59/7/10.1007/s11432-016-5588-7?slug=abstract this paper] seems to use the term "Sunway" for both the CPU and supercomputer architecture; since this appears |
| 2016-06-29 11:13 | Diff · History | 445 | →Paper: == "Sunway" vs. "ShenWei" == In the article, both the names "Sunway" and "ShenWei" are used to describe computer/chip architectures. Are these, in fact, actually the same term in Chinese, and if so, should we settle on one particular standard |
| 2016-06-24 08:51 | Diff · History | 34 | {{WikiProject Computing|hardware=yes|hardware-importance=}} |
| 2016-06-22 10:17 | Diff · History | 69 | →Paper: more |
| 2016-06-22 10:17 | Diff · History | 92 | →Paper: That would make sense: why use ASIC logic to do this when you already have CPUs everywhere? |
| 2016-06-22 10:16 | Diff · History | 195 | →Paper: ::Reading the paper, it looks like they're taking a software, not hardware, approach to synchronization. -- ~~~~ |
| 2016-06-22 10:08 | Diff · History | 110 | →Paper: and I also wonder if it and the network-on-a-chip have been explicitly designed to work together? |
| 2016-06-22 10:04 | Diff · History | 149 | →Paper: The interconnect is going to be very interesting: I wonder if it has things like cache-coherency logic and synchronization primitives built into it? |
| 2016-06-22 10:01 | Diff · History | 461 | →Paper: ::Yes, it's absolutely fascinating. I think the Chinese team have done something extremely clever here; this is a very nice half-way-house between a conventional NUMA cache-coherent CPU cluster architecture and a GPU-like architecture, and if |
| 2016-06-22 09:19 | Diff · History | 14 | GPU-core-like |
| 2016-06-22 09:14 | Diff · History | 857 | Reading the paper: it looks like they use OpenACC 2.0 for parallelization of code. Very nice. The SW26010 chip also has DDR3 controllers on it, so main memory hangs directly off the CPU chips. It also looks like the local per-core scratchpad can be us |
| 2016-06-22 09:00 | Diff · History | 10 | Paper |
| 2016-06-22 08:51 | Diff · History | 16 | There's a paper being published about this,... |
| 2016-06-22 08:49 | Diff · History | 200 | Open access here: http://engine.scichina.com/publisher/scp/journal/SCIS/59/7/10.1007/s11432-016-5588-7?slug=abstract . It also looks like the paper may be free content: it has a watermark saying "All article content, except where otherwise noted, is lice |
| 2016-06-22 08:46 | Diff · History | 82 | Open access here: http://engine.scichina.com/publisher/scp/journal/SCIS/59/7/10.1007/s11432-016-5588-7?slug=abstract |
| 2016-06-22 08:44 | Diff · History | 387 | There's a paper on the way, according to Jack Dongarra's report: “The Sunway TaihuLight Supercomputer: System and Applications”, by Fu H H, Liao J F, Yang J Z, et al., to appear in Sci. China Inf. Sci., 2016, 59(7): 072001, doi: 10.1007/s11432-016-5 |
| 2016-06-20 10:54 | Diff · History | 13 | {{reqphoto}} |
| 2016-06-20 10:29 | Diff · History | 47 | {{WikiProject Computers}} {{WikiProject China}} |
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