Top edits to an page
All edits made to a page by one user, in chronological order.
Page | RISC-V (Log · Page History) |
User | Guy Harris (Edit Counter· Top Edits) |
Total edits | 203 |
Minor edits | 0 (0%) |
(Semi-)automated edits | 14 (6.9%) |
Reverted edits | 2 (1%) |
atbe1 | 13.5 |
Added (bytes)2 | 10,085 |
Deleted (bytes) | -2,649 |
Minor edits
·
0 (0%)
Major edits
·
203 (100%)
(Semi-)automated edits
·
14 (6.9%)
Manual edits
·
189 (93.1%)
Reverted edits
·
2 (1%)
Unreverted edits
·
201 (99%)
1 Average time between edits (days)
2 Added text is any positive addition that wasn't reverted (approximate)
Date | Links | Size | Edit summary |
---|---|---|---|
2024-09-05 22:58 | Diff · History | 8 | Change domain name to match what their certificate says. |
2024-09-05 22:46 | Diff · History | -9 | Remove extra URL crud. |
2024-09-05 21:01 | Diff · History | 0 | →Software: Improve tone. |
2024-09-05 21:00 | Diff · History | 0 | →Existing: Remove unnecessary underscore from wikilink. |
2024-09-05 20:54 | Diff · History | -26 | →Open source: Again, no person I know of is named "heise online". |
2024-09-05 20:43 | Diff · History | 32 | The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA, Document Version 20191213, appears to be released under a Creative Commons license, not a BSD license. |
2024-09-05 20:39 | Diff · History | -26 | →Implementations: "online" is not a common family name; the article was not written by a member of the "online" family with the given name "heise". |
2024-09-05 20:36 | Diff · History | 22 | Link system on a chip. Pluralize SoC. |
2024-09-05 20:34 | Diff · History | 6 | Not all RISC-V International members offer hardware, as not all RISC-V International members are hardware designers; they may be software developers. Use "and" before the last member of a list of those who *are* designing SoCs. |
2024-09-05 20:31 | Diff · History | -115 | Just give the page title, not the introductory text, as the title of the reference. |
2024-09-05 20:27 | Diff · History | 3 | Use "such as" to introduce a list of examples. |
2024-09-05 20:08 | Diff · History | 33 | →Software: Link Scala. |
2024-09-05 20:07 | Diff · History | 4 | →Software: An article is needed there. |
2024-09-05 20:05 | Diff · History | -5 | →Software: ce |
2024-09-05 20:00 | Diff · History | -6 | →History: Remove unnecessary "While". |
2024-04-09 07:02 | Diff · History | -26 | →Existing: No need to link "XXX ports" if XXX is a page. "Serial Peripheral Interface" is a standard, making it a proper name, so capitalize the first letters of each word. |
2023-12-04 17:39 | Diff · History | 145 | Use the Wayback Machine for a link that now just asks you to log in. |
2023-12-04 17:34 | Diff · History | -1 | Once again, WindowServer plus the unhelpful Wikipedia JavaScript-based editor strike again, dumping a keystroke into the page rather than the Safari search box. |
2023-12-04 17:33 | Diff · History | 133 | Use the Wayback Machine for a link that appears to just keep spinning. |
2023-12-01 08:12 | Diff · History | 14 | →History: MOS:HYPHEN ("free-software" is a compound modifier, not a noun, here). |
2023-12-01 08:01 | Diff · History | -8 | The name does not appear to be SHOUTED IN ALL CAPS. |
2023-12-01 07:50 | Diff · History | -17 | MOS:SUBMARINE. If the section were to explicitly mention Switzerland's political neutrality, that explicit mention could and probably should link to Swiss neutrality - e.g., if it were to say "because of its political neutrality - but "Switzerland", by itself, should link to the page for the country. |
2023-12-01 07:41 | Diff · History | 54 | →Compressed subset: Link "MIPS16" to MIPS architecture#Application-specific extensions. |
2023-12-01 07:33 | Diff · History | -13 | →Compressed subset: Copyedit. Alias (computing) refers to a very specific type of aliasing, for memory references, unrelated to the "aliasing" described here. Refer to it, instead, as alternative encodings for the instructions in the compressed set. |
2023-09-27 11:37 | Diff · History | -1 | →Open source: Get rid of extra blank line. |
2023-09-27 11:36 | Diff · History | 788 | Undid revision 1177385997 by 145.52.147.213 (talk) - rv damage |
2023-09-07 10:19 | Diff · History | -1 | →History: Get rid of extra newline. |
2023-07-19 06:24 | Diff · History | 389 | →Memory access: Mention that the privileged ISA allows an implementation to be little-endian, big-endian, or bi-endian. |
2023-05-10 06:30 | Diff · History | 6 | A Google search for "rv5" site:riscv.org found nothing, so it appears not to be an official term, and at least one person who asked on the talk page what it means. It appears to mean "RISC-V", so just replace it with "RISC-V". |
2023-05-10 05:12 | Diff · History | 61 | →ISA base and extensions: I guess the "I" in "IMAFDZicsr_Zifencei" means "RV{32,64}I", excluding the embedded version. Speaking of embedded, put a space before the "(embedded)" in the description of RV64E. |
2023-05-10 05:07 | Diff · History | 39 | →ISA base and extensions: Use that as a reference for "G" being short for "IMAFDZicsr_Zifencei". (OMGWTFLOLBBQ) |
2023-05-10 04:57 | Diff · History | 41 | →ISA base and extensions: And here's the reference. ("...'general-purpose' ISA...") |
2023-05-10 03:33 | Diff · History | 100 | →ISA base and extensions: Apparently, it includes one of the RV bases, the G collection of extensions, and the C extension. I'll use Chapter 24 of the unprivileged spec as a reference in a subsequent edit. Oh, and don't use "RVGC" as a noun, as the explanation of the letter cluster still laves it not obvious what it means if used as a noun; use it as an adjective modifying "instruction set". |
2023-04-14 21:55 | Diff · History | -20 | Avoid redirect. |
2023-02-07 08:14 | Diff · History | 19 | Separate non-reference footnotes for the "ISA and extensions" table from non-reference footnotes for the article as a whole. |
2023-01-28 23:37 | Diff · History | 23 | →RISC-V Foundation and RISC-V International: There's nothing on the DAC home page about that. Perhaps this is referring to her involvement with the OpenPOWER Foundation (although she may have been more involved with z/Architecture systems than with Power ISA systems). |
2023-01-28 23:22 | Diff · History | 19 | →Embedded subset: Add the date of the message (in case the joke wasn't obvious enough). |
2023-01-28 23:19 | Diff · History | 177 | Use the Wayback Machine for a now-dead link. Update some URLs, and fix the title and author of one link. |
2023-01-28 22:46 | Diff · History | -18 | Update URL, make title match what the article has. |
2023-01-28 22:44 | Diff · History | 156 | Use the Wayback Machine for a now-dead link. |
2023-01-28 22:32 | Diff · History | 23 | Mark a dead link as such. |
2023-01-28 22:14 | Diff · History | 61 | Use the scalar crypto spec as a reference for the instruction count. |
2023-01-28 22:10 | Diff · History | 14 | →Bit manipulation: Wolf is listed as the editor; there's a big pile of contributors, including Wolf, on the page after the title page. |
2023-01-28 22:02 | Diff · History | 449 | →Bit manipulation: Expand an incomplete clause, and point to the scalar crypto spec as the new home of some of the more specialized instructions. |
2023-01-28 20:48 | Diff · History | -2 | →Bit manipulation: Copyedit. |
2022-09-18 20:28 | Diff · History | -1 | →Arithmetic and logic sets: Get rid of extra blank line. |
2022-09-11 06:52 | Diff · History | -2 | →ISA base and extensions: The reference says it's frozen and speaks of ratification as something that hasn't happened yet. |
2022-09-07 21:03 | Diff · History | -130 | →Vector set: The vector extension is up to 1.0. |
2022-09-07 19:51 | Diff · History | 41 | →Vector set: Naked URLs are ugly. Please drape them. (BTW, this is a draft of 0.*9*, if the title page is to believed.) |
2022-09-07 19:50 | Diff · History | -4 | →Vector set: "version 0.8" suffices; no need for "the" before "versi |
2022-09-07 19:48 | Diff · History | 0 | →Vector set: Period at end of sentence. Remove space before reference. |
2022-08-12 23:43 | Diff · History | 185 | Use the Wayback Machine for a now-dead link. Mark another link as dead. |
2022-08-12 23:18 | Diff · History | 6 | That's a conference paper. Use {{cite conference}} |
2022-08-12 23:12 | Diff · History | 210 | Use the Wayback Machine for a now-dead link. |
2022-08-12 22:31 | Diff · History | 341 | Use the Wayback Machine for now-dead links. |
2022-08-08 07:20 | Diff · History | -531 | Point to the current privileged ISA specification, 1.12, for all privileged ISA references. Update the date and version of the latest ratified version. |
2022-08-08 06:25 | Diff · History | 17 | →Rationale: And explicitly mark it as dead. |
2022-08-08 06:24 | Diff · History | 151 | Use the Wayback Machine for a now-dead link. |
2022-08-08 06:09 | Diff · History | 1 | →Software: And another conference paper that needs to be cited with {{cite conference}}. |
2022-07-25 20:55 | Diff · History | -1 | →Software: And another space. |
2022-07-25 20:54 | Diff · History | -16 | →Software: Get rid of space before references. |
2022-07-06 01:18 | Diff · History | 129 | →Software: What sort of "middleware" is that? A lot of "middleware" doesn't care much, if at all, what ISA it's running on; it cares more about what OS it's running on. |
2022-07-01 02:58 | Diff · History | -1 | Get rid of stray trailing # in URL. |
2022-07-01 02:05 | Diff · History | 284 | →In development: Use {{cite journal}} for the Microprocessor Report article, and get rid of bogus dates. Also provide an EE Times reference. |
2022-05-17 02:45 | Diff · History | 1 | →ISA base and extensions: ce alt text |
2022-05-17 02:37 | Diff · History | 21 | →ISA base and extensions: Give the full name of the extension in the alt text, just as we do in the caption. (P.S. black on dark blue is... not the best color combination for older eyes. Contrast Is Your Friend.) |
2022-05-16 06:55 | Diff · History | -2 | →ISA base and extensions: Get rid of extra blank line. |
2022-05-09 21:01 | Diff · History | -20 | Undid revision 1086957620 by 81.255.42.139 (talk) - openness and freedom are part of the rationale for RISC-V; the section discusses the entire rationale, so "Rationale" suffices. |
2022-03-23 00:00 | Diff · History | 33 | Rewrite to try to make it a bit clearer what it is that's being set up to simplify the use of multiplexers. |
2022-03-22 23:56 | Diff · History | 37 | Link "multiplexers" so people can click it to find out to what it refers. |
2022-01-10 01:27 | Diff · History | -27 | Undid revision 1064733480 by UserTwoSix (talk) - RISC-V is RISC, not CISC, and wasn't designed in reaction to CISC, so it's not obvious why it's relevant. (Nobody other than Intel, AMD, and IBM are designing new CISC CPUs for general-purpose computing these days.) |
2022-01-09 23:03 | Diff · History | -27 | Undid revision 1064727855 by UserTwoSix (talk) - Arm Ltd. and the ARM architecture are both mentioned earlier in the article (and there's no "ARM CPU", there are many CPU cores, designed by Arm Ltd. and others, that implement different versions of the ARM architecture). |
2022-01-09 23:00 | Diff · History | -15 | Undid revision 1064728909 by UserTwoSix (talk) - either "RISC-V" stands for "RISC five" or it doesn't stand for anything. Yes, "RISC" in "RISC-V" stands for "reduced instruction set computer", but it's no more notable as a RISC than any other RISC ISA. |
2021-12-27 21:18 | Diff · History | 341 | →Software: That's a conference paper; use {{cite conference}}, and fill it in further. |
2021-12-27 21:02 | Diff · History | 154 | →Existing: Fix title for reference, add more parameters. |
2021-11-20 04:34 | Diff · History | 4 | →Software: "allows the user". |
2021-11-08 05:05 | Diff · History | 47 | →Open source: Spell out "lookup table" and link it to lookup table#Hardware LUTs, for the benefit of those unfamiliar with the term in this context. |
2021-11-08 02:25 | Diff · History | 0 | →Open source: Punctuation before references. |
2021-11-08 02:23 | Diff · History | 32 | →Open source: "MIPS" isn't the plural of "MIP", it's an acronym for "millions of instruction per second". And MIPS, like MIP, is a disambiguation page; link to million instructions per second. (And it doesn't necessarily literally mean the number of millions of instructions that are executed in a second, but I digress....) |
2021-11-08 02:04 | Diff · History | 53 | →Compressed subset: I guess page 99 of the current spec is the right reference for that. Clarify that it's large code size than in other instruction sets *with variable-length instructions*. |
2021-11-08 01:47 | Diff · History | 102 | →Rationale: Convert some references to use the current specification and to give a location in the specification. Rewrite the bit about the variable-length ISA and extensions to make it clear what it means (the variable-length capabilities don't *provide* extensions, they provide room *for* extensions |
2021-11-07 23:52 | Diff · History | 0 | →Atomic memory operations: That implementor's note is in the 2.2 spec as well; point to that rather than the one in the 2.1 spec. |
2021-11-07 23:45 | Diff · History | 51 | →Atomic memory operations: I presume this is the example to which the last paragraph is referring (it's only one example, the other example is a compare-and-swap). |
2021-11-07 23:28 | Diff · History | 14 | →Atomic memory operations: OK, that one's *not* in the current unprivileged spec, but *is* in the 2.1 spec. Give a page number in *that* spec. |
2021-11-07 23:14 | Diff · History | 207 | Use named parameters with {{rp}}, as recommended. |
2021-11-07 23:00 | Diff · History | 239 | →Subroutine calls, jumps, and branches: Use the current unprivileged spec, and give section numbers, for most references. RV64I also reserves a HINT instruction space that's a superset of the RV32I space. |
2021-11-07 22:46 | Diff · History | -32 | →Embedded subset: Point to chapter 4 of the current specification. That chapter does *not* forbid adding the floating-point extension, although it does say that an alternative extension using the integer registers is being considered. It says nothing about compressed instructions (other than the implied "all standard extensions may be used", which includes C). |
2021-11-07 22:28 | Diff · History | 176 | →Atomic memory operations: Use the current version of the unprivileged spec, and give page or chapter numbers, for most of the references. |
2021-11-07 22:00 | Diff · History | 175 | →Arithmetic and logic sets: For the "no arithmetic exceptions" stuff, cite the current version of the unprivileged spec, and give page numbers for the various claims. "The status bits can be tested by an operating system or periodic interrupt." isn't explicitly stated, so don't attach a reference to it. |
2021-11-07 21:40 | Diff · History | 23 | →Arithmetic and logic sets: Use the latest spec, and give page numbers, for the floating-point instructions. The bit about machines without-floating point using a software library isn't in the document, but it's somewhat of a "no, duh!" statement, given how many generations of computer have done exactly that. |
2021-11-07 21:34 | Diff · History | 23 | →Arithmetic and logic sets: Use the latest spec, and give page numbers, for the integer multiply and divide instructions. |
2021-11-07 21:30 | Diff · History | 14 | →Immediates: Update another reference to the current version of the unprivileged spec and give it a page number. |
2021-11-07 21:20 | Diff · History | 14 | →Memory access: I *guess* the note on page 16 covers the rationale for the 12-bit offset. |
2021-11-07 21:14 | Diff · History | 120 | →Memory access: Put all the byte-order stuff together, and update it to reflect the current reality, in which big-endian access to data can be supported. |
2021-11-07 21:04 | Diff · History | 37 | →Memory access: State the examples of CISC ISAs without addressing modes that modify registers in a better fashion. |
2021-11-07 21:02 | Diff · History | 14 | →Memory access: Point to the load/store instructions section of the current unprivileged spec for the lack of register-modifying address modes (it's not explicitly stated that they don't exist, but the section doesn't describe any). |
2021-11-07 21:01 | Diff · History | 68 | →Memory access: For alignment requirements, use the current version of the unprivileged spec. That version of the spec says that an execution environment interface may allow unaligned accesses or may cause a (visible) exception for unaligned accesses. |
2021-11-07 20:44 | Diff · History | 7 | →Memory access: Parallel construction. |
2021-11-07 20:42 | Diff · History | 170 | →Memory access: For the byte order, use the current version of the unprivileged spec. That version of the spec says that both little-endian and big-endian execution environment interfaces are supported. |
2021-11-07 20:19 | Diff · History | 14 | For the formation of addresses in load and store instructions, use the current unprivileged ISA spec, and give a page number. Use that reference only for the way addresses are formed, not for the explanatory text (an ISA spec doesn't need to explain those details, and this one doesn't appear to do so). |
2021-11-07 20:03 | Diff · History | 23 | →Subroutine calls, jumps, and branches: So where in either the 2.1 or current unprivileged ISA spec do they specifically state that a compressed instruction set will solve the problem of code without predication being larger (rather than just stating the obvious, namely that it reduces code size in general)? |
2021-11-07 19:42 | Diff · History | 21 | Refer to the current unprivileged spec's compressed instructions section, rather than to the draft compressed instructions spec extracted from an earlier unprivileged spec, in most cases. |
2021-11-07 19:25 | Diff · History | 39 | For the compressed instructions extension (the spec calls it that, not the "compact" extension), use the current unprivileged spec, and give a page number range. |
2021-11-07 19:16 | Diff · History | 14 | For the 128-bit version, use the current unprivileged spec, and give a page number (that's Chapter 6 "RV128I Base Integer Instruction Set, Version 1.7"). |
2021-11-07 19:11 | Diff · History | 23 | For the variable-length encoding, use the current unprivileged spec, and give page numbers (that's section 1.5 "Base Instruction-Length Encoding"). |
2021-11-07 18:03 | Diff · History | 49 | According to page 18 of the current unprivileged ISA spec, the "MV" assembler pseudo-op, presumably being "MoVe", is done with add immediate, not add. |
2021-11-07 17:33 | Diff · History | 16 | Give pages for more references to the current unprivileged ISA specification (reduces the search space for the text supporting the claim by a factor of approximately 220). |
2021-11-07 17:25 | Diff · History | 485 | Point to the external debug spec. |
2021-11-07 07:16 | Diff · History | 402 | Fix the privileged architecture specification. |
2021-11-07 06:35 | Diff · History | 126 | Rename the 2.1 reference to "isa2.1", as it's not *THE* ISA, it's the 2.1 version of the (base user-level) ISA, which isn't the latest shiniest version. |
2021-11-07 06:33 | Diff · History | 16 | Point some more references to the latest user-mode spec. |
2021-11-07 06:07 | Diff · History | 479 | OK, here's where the 2.2 spec is hiding. When https://riscv.org/technical/specifications/ isn't your friend, https://www.google.com is. |
2021-11-07 06:02 | Diff · History | -18 | OK, where's version 2.2 hiding? It's *not* Technical Report No. UCB/EECS-2016-118 - that's 2.1 - and it's not the current spec, as that's 20191213, which lists some substantial changes made since the 2.2 spec (e.g., "Changed description of misaligned load and store behavior."). |
2021-11-07 05:55 | Diff · History | 58 | →References: UCB technical report EECS-2016-118 is not 2.2, it's 2.1 (it says so right on the cover page!), and there's a direct link to it - use it. |
2021-11-07 05:52 | Diff · History | 63 | Fix some references to point to the "current, ratified" version of the unprivileged ISA spec. and fix that reference. (The spec references need some cleanup work.) |
2021-11-07 05:30 | Diff · History | -14 | I guess the second paragraph of the footnote on page 17 is the reference for the other claim. |
2021-11-07 05:28 | Diff · History | 9 | That particular claim is supported by text on page 17 of the current user-mode spec. |
2021-11-07 05:05 | Diff · History | 23 | OK, where in the ISA specification does it say anything about bit patterns in instructions chosen to minimize the number of multiplexors? See talk page. |
2021-10-10 18:52 | Diff · History | 6 | Request a citation for "bit patterns to simplify the multiplexors" (instruction bit patterns?). |
2021-10-10 18:17 | Diff · History | 79 | Being load-store isn't particularly notable about an architecture that has "RISC" in its name. Using IEEE 754 isn't particularly notable about an architecture designed after IEEE 754 was introduced. Copyedit the remaining ISA features that *aren't* expected of, and present in, all RISC architectures. |
2021-09-30 21:35 | Diff · History | -1 | →Existing: No space between end-of-sentence period and reference. |
2021-09-30 21:34 | Diff · History | -2 | →Existing: Remove stray "P". |
2021-08-17 18:46 | Diff · History | -66 | Undid revision 1039251951 by 90.56.15.130 (talk) - yes, it began as a RISC project at Berkeley, but it lacks one of the most significant characteristics of Berkeley RISC, namely register windows, so calling it based on Berkeley RISC is a bit of an overstatement. |
2021-07-10 19:16 | Diff · History | 87 | (reverted) Undid revision 1032852150 by 89.107.6.68 (talk) - it's three separate fields, not one single field. |
2021-06-23 19:59 | Diff · History | -10 | Get rid of unnecessary piping. |
2021-05-12 19:45 | Diff · History | 40 | →Software: Put Debian and Fedora together as Linux distributions, with Haiku mentioned separately. (The parenthetical note says "both", but "32-bit or not?" should be given for the various BSDs and Haiku, not just for Debian and Fedora. |
2021-05-12 19:40 | Diff · History | 109 | →Software: Haiku has a Wikipedia page; link to it. Use the external link as a reference. No need to express surprise at a Haiku port. |
2021-03-19 09:50 | Diff · History | -17 | Undid revision 1012965913 by 201.175.156.244 (talk) - WP:WTAF, MOS:NOTSEEALSO. |
2021-03-06 22:12 | Diff · History | -2 | That's not a RISC-V processor, it's a development tool for RISC-V processors. Add a section for them. One link to Lauterbach per paragraph suffices. Move another trace solution there as well. |
2021-01-09 18:16 | Diff · History | 1 | ce |
2020-12-21 23:21 | Diff · History | 90 | →References: This is the way to use an archiving site. |
2020-11-18 02:29 | Diff · History | -126 | Undid revision 989275668 by 67.161.49.3 (talk) - that belongs in an article about Micro Magic; perhaps either the existing Micro Magic article should be expanded (if that's the EDA company mentioned at the end of the last paragraph), or a separate article for the new Micro Magic should be written, with the article about the old Micro Magic linking to it. |
2020-10-15 18:05 | Diff · History | -2 | →History: Fix formatting. |
2020-08-27 19:20 | Diff · History | -2 | Punctuation, but no space, before references. |
2020-07-12 22:41 | Diff · History | -29 | Clean up references to the RISC-V ISA Developers mailing list. |
2020-04-01 16:50 | Diff · History | 2 | →Software: ce to make it clearer; move the reference to refer to the specific claim (their home page mentions "RISC-V64 (64 bits)" in its list of supported ISAs). |
2020-01-31 01:45 | Diff · History | 5 | Spell the endianness out, as is done for other ISAs. |
2020-01-31 00:29 | Diff · History | 25 | Give a reference for "RISC five". |
2020-01-13 23:26 | Diff · History | 113 | →Bit manipulation: OK, what's the *current status* of the review; January 2020 isn't over yet. |
2020-01-13 20:03 | Diff · History | -6 | →History: No need for any extra space at the end of a paragraph. |
2019-12-28 01:52 | Diff · History | -179 | That sentence is about DLX, not RISC-V; DLX isn't supported by LLVM, as far as I know. |
2019-12-17 18:13 | Diff · History | -1 | →Rationale: Remove extra period. |
2019-12-15 22:24 | Diff · History | 44 | →Rationale: I've read ARM and MIPS ISA documentation online without signing an ISA. Citation needed on that part of the claim. |
2019-11-28 16:45 | Diff · History | -2 | Undid revision 928325572 by Walkeer (talk) - and that's not what it was saying; it was saying it was the first OoO *RISC-V* implementation. |
2019-11-14 17:44 | Diff · History | 164 | →In development: Naked URLs are ugly. Please drape them. Copyedit. |
2019-11-02 16:37 | Diff · History | -96 | →Rationale: Remove redundant statement (it's almost identical to the first sentence of the paragraph, except that it replaces "harder" with "much more difficult"). |
2019-10-15 01:09 | Diff · History | 0 | Fix capitalization. |
2019-10-05 18:08 | Diff · History | -7 | →Subroutine calls, jumps, and branches: Some do, some don't. Why do MIPS and SPARC count as "traditional", while POWER doesn't? |
2019-09-04 03:23 | Diff · History | -18 | →References: That project now has its domain. |
2019-09-03 20:32 | Diff · History | 90 | →Further reading: No, it's just that {{cite web}} now requires website=, so give it some. |
2019-09-03 20:27 | Diff · History | -3 | →External links: No need to select a particular national version of Google Scholar. |
2019-09-03 20:25 | Diff · History | -2 | →External links: Apparently, publisher= by itself is not OK for some citation templates these days, without indicating what's being published with website=/newspaper=/etc. |
2019-09-03 19:02 | Diff · History | 11 | →Commercial: ce |
2019-08-11 17:48 | Diff · History | -2 | →Privileged instruction set: ce previous edit |
2019-08-11 17:48 | Diff · History | 72 | →Privileged instruction set: Or perhaps to run something *other* than Linux; Linux is not the only operating system in the universe, and not even the only open-source portable operating system in the universe. |
2019-08-11 17:45 | Diff · History | 37 | Remove extra comma, use both the 2.2 user-mode ISA spec and the 1.11 privileged ISA spec as reference in both the infobox and the lede. |
2019-08-11 17:43 | Diff · History | 6 | ce |
2019-07-30 19:58 | Diff · History | -151 | →Commercial: Citation requested for the T-Head processor, and none provided; meanwhile, somebody provided a citation for a RISC-V chip from Alibaba Group, without any mention of "T-Head". Remove the T-Head item. |
2019-07-30 19:54 | Diff · History | -47 | →Commercial: You don't externally link to Wikipedia pages, you wikilink them. The phrase is just "to date", not "to the date". No space before reference. |
2019-07-20 18:12 | Diff · History | -3 | →Commercial: There's nothing to attribute there. Presumably they meant "*Citation* needed". |
2019-07-20 18:08 | Diff · History | 4 | →Commercial: Boston University? :-) Spell out "business unit". Link Alibaba Group rather than throwing in their New York Stock Exchange symbol. |
2019-05-23 07:34 | Diff · History | -16 | →Commercial: "C-STAT included" what? Fill that in, and give a citation. |
2019-05-14 16:09 | Diff · History | -3 | →Predecessors: ce |
2019-03-15 06:43 | Diff · History | 0 | →History: Sentence case in section headings. |
2019-03-14 20:37 | Diff · History | 81 | →Software: Link TianoCore and Hewlett Packard Enterprise, and give the GitHub repository for the TianoCore port as a reference. |
2018-12-24 03:09 | Diff · History | 0 | →Arithmetic and logic sets: Fix typo. (Presumably you do a divide followed by a test-whether-the-divisor-is-zero-and-branch.) |
2018-12-24 01:41 | Diff · History | 5 | →ISA base and extensions: Use {{cite AV media}} for YouTube videos. |
2018-11-30 20:07 | Diff · History | 269 | →Commercial: Give citation for GAPuino shipping. |
2018-11-16 21:39 | Diff · History | 4 | →Commercial: English requires "its" there. |
2018-11-16 21:38 | Diff · History | 0 | →Commercial: More punctuation-before-references. |
2018-11-16 21:37 | Diff · History | -1 | →Commercial: Punctuation before references. |
2018-11-16 21:37 | Diff · History | -12 | →Commercial: A "Linux core" is presumably a CPU core that melts down and destroys the universe if you try to run something other than Linux on it. The first reference doesn't mention Linux, and the second mentions it only in passing, so.... |
2018-10-18 19:49 | Diff · History | -39 | Template:Infobox CPU architecture doesn't have a "homepage" parameter, so adding "homepage = " has no effect. |
2018-10-18 19:48 | Diff · History | -141 | So who has confused it with ARM? (And who didn't notice the description of it as an open standard in the first two paragraphs?) |
2018-09-25 06:29 | Diff · History | 11 | →Significance: Clean up references. |
2018-09-24 17:05 | Diff · History | 42 | It was better before (https://www.quickanddirtytips.com/education/grammar/like-versus-such-as for "such as" vs. "like", {{as of}} indicates that the claim may need to change in the future, and "by" somewhat implies that something happened at that point). |
2018-09-11 19:49 | Diff · History | -15 | →Commercially available: They're still producing it. |
2018-09-07 02:57 | Diff · History | 3 | →Significance: I guess that's one reason why they call it "SemiAccurate" - their spelling isn't 100% accurate. :-) (Yes, the headline really *does* get it wrong.) |
2018-08-31 07:52 | Diff · History | 22 | Undid revision 857364692 by 73.231.30.41 (talk) - the offset *is* multiplied by 2, as it's in units of 2-byte parcels, not bytes. |
2018-08-25 05:44 | Diff · History | 163 | (reverted) →Register sets: RISC-V wasn't the first RISC ISA to have a wired-to-zero register. |
2018-08-25 05:38 | Diff · History | 1 | →Register sets: ce |
2018-08-25 05:37 | Diff · History | -4 | →ISA base and extensions: Remove noise. |
2018-08-02 18:33 | Diff · History | -237 | →References: Remove no-longer-used reference. |
2018-08-02 18:30 | Diff · History | -87 | No need to paste the main website all over the page. |
2018-07-14 19:12 | Diff · History | 181 | →Foundation: Citation for Andes Technology being a supporter - and founding member - of the foundation. That gives a link to their site, in case somebody wants one. |
2018-04-23 16:33 | Diff · History | -37 | →Software: The GPL isn't software, so something might be GPL-licensed, but not GPL-based. In any case, if somebody cares about the QEMU license, the page for QEMU should give that detail. |
2018-04-23 16:32 | Diff · History | -26 | →Software: Punctuation before references. Leave out licensing details of Renode - if somebody cares they can go look at its website, and it removes a comma-separated list from the comma-separated list. |
2018-04-20 11:33 | Diff · History | -1 | →Memory access: Remove extra newline added incorrectly. |
2018-03-26 21:10 | Diff · History | 102 | →Memory access: Note that (at least) two significant CISC ISAs also lack address modes that modify registers. |
2018-03-21 20:55 | Diff · History | 29 | →Foundation: Use {{cite web}}. |
2018-02-19 18:07 | Diff · History | -4 | Undid revision 826499641 by 185.27.49.90 (talk) - WP:WTAF. |
2018-01-21 20:59 | Diff · History | 5 | →Awards: More like a publisher. |
2018-01-09 19:15 | Diff · History | 0 | Undid revision 819457057 by 141.7.148.61 (talk) - punctuation *before* references; see MOS:PUNCTREF. |
2018-01-08 09:04 | Diff · History | -34 | Undid revision 819239086 by Lopifalko (talk) - explaining "instruction set architecture" is non-technical terms is the job of the instruction set architecture page. |
2018-01-02 20:58 | Diff · History | -11 | →Foundation: The other reference doesn't mention the foundation, so maybe HPE and Oracle are supporters in some way other than being members of the foundation. |
2018-01-02 20:53 | Diff · History | -36 | →Foundation: Say "BAE Systems", not just "BAE". Add {{cn}} to all organizations not listed on the "members at a glance" page. The Rambus reference isn't needed - the "members at a glance" page lists them (complete with "Cryptography Research"). |
2018-01-02 20:44 | Diff · History | 137 | →Foundation: Give the "members at a glance" page as a reference for the list of organizations. |
2017-11-28 21:39 | Diff · History | 0 | →Memory access: "n-bit", as an adjective, is hyphenated. "n bits", as a phrase, is not. |
2017-09-18 04:54 | Diff · History | 2 | →Atomic memory operations: Commas to make it read more clearly. (As for IBM i, yes, MI has a compare-and-swap operation, but nobody ever built a machine that directly executed it - it's a virtual instruction set, like the JVM instruction set.) |
2017-09-18 02:20 | Diff · History | -13 | →Atomic memory operations: Actually, PPC does ll/cs. |
2017-09-18 02:17 | Diff · History | -5 | →Atomic memory operations: Presumably by IBM i you meant PowerPC (perhaps IMPI also had it, given that it was S/370-like). |
2017-09-18 02:15 | Diff · History | 72 | →Atomic memory operations: The CAS opcode comes from S/370; it has compare-and-swap. Link compare-and-swap. |
2017-02-27 20:53 | Diff · History | -18 | →Subroutine Calls, Jumps and Branches: "its", not "it's", for possessive. For now, the article is called branch predication, not "predication (computer architecture)". |
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