Dual-ported video RAM (VRAM) is a dual-ported variant of dynamic RAM (DRAM), which was once commonly used to store the framebuffer in graphics adapters.

Dual-ported RAM allows the CPU to read and write data to memory as if it were a conventional DRAM chip, while adding a second port that reads out data. This makes it easy to interface with a video display controller (VDC), which sends a timing signal to the memory and receives data in the correct sequence as it draws the screen. Because the CPU and VDC access the memory simultaneously on different ports, dual-ported RAM does not require the CPU to pause while the VDC uses memory, thereby eliminating the associated wait states and improving overall system performance.

Dual-ported RAM was common from the mid-1980s into the mid-1990s. After that date, new forms of high-performance memory began to be used that eventually replaced dual-ported designs. As these other forms of memory are also known as video memory, and thus VRAM, it sometimes confused with this older form of memory.

Early computers used dynamic RAM^[a] to store video data to be output to a conventional television or a simple conversion of a television that accepted composite video input. To work with such a display it is extremely important that the video hardware output a very accurately timed signal. At the speeds that contemporary memory worked at, reading data to feed to the video hardware used up much of the possible performance of the memory devices. This conflicted with the need for the central processing unit (CPU) to write data to memory for the video system to read, as both could not use the same memory at the same time.

Two general solutions were used to avoid timing issues. For higher-priced systems, the video systems had their own dedicated memory and used a separate system for the CPU to store data into it. This eliminated any possibility of contention for memory, but at the cost of requiring separate memory in an era when memory was very expensive. It also almost always communicated over a slow system bus that limited the speed that changes to the screen could be made, making interactive graphics difficult. The other solution, used by most home computers, was to use a single shared bank of memory and allow the video hardware to control access to memory, pausing the CPU when needed. This may lead to slower computing performance as the CPU is repeatedly put into these "wait states", but it had the advantage of being less expensive and allowing the CPU to more rapidly update the display and thus provide more interactivity.

By the early 1980s, the introduction of much higher-resolution monitors that demanded larger framebuffers, and the newly introduced graphical user interfaces (GUIs) that required high resolution and high overall performance, made the performance of the video system an increasingly difficult problem. Complex systems like the Amiga Agnus emerged to carefully control access to memory and reduce contention, but while these reduced the problem they did not eliminate it.

The solution was to use memory that could be accessed by the CPU and video hardware at the same time. It was invented by F. Dill, D. Ling and R. Matick at IBM Research in 1980, with a patent issued in 1985 (US Patent 4,541,075).^[1] The first commercial use of VRAM was in a high-resolution graphics adapter introduced in 1986 by IBM for its RT PC system, which set a new standard for graphics displays. Prior to the development of VRAM, dual-ported memory was quite expensive, limiting higher resolution bitmapped graphics to high-end workstations. VRAM improved the overall framebuffer throughput, allowing low cost, high-resolution, high-speed, color graphics. Modern GUI-based operating systems benefitted from this and thus it provided a key ingredient for proliferation of graphical user interfaces (GUIs) throughout the world at that time.

Dynamic RAM is internally arranged in an array of rows and columns of capacitors, with each row/column intersection holding a single bit in a cell. In typical use, a CPU accessing a DRAM will ask for a small amount of data at a time, possibly a single byte. To read a byte for the CPU, the DRAM decodes the provided address into a series of eight cells, reads the entire row containing those cells, and latches the requested data so it can be read on the data bus. At the time, rows were commonly 1,024 cells wide.

DRAM devices are destructive, meaning that the act of reading a row also causes the data in it to be erased. To make the data permanent, any reading has to be followed by the DRAM writing the same data back to that row. To accomplish this, separate latches for the entire row have to be included, and the data is written back to the row while the CPU is reading out the requested byte. When one considers the process as a whole, this means the DRAM is repeatedly reading entire rows of data, selecting a single byte from that data and discarding the rest, and then writing it all back again.

VRAM operates by not discarding the excess bits in the row. Instead, the data read into the row storage is also sent to a second set of latches and an associated bit shifter. From that point, the data can be read out a bit at a time by triggering the shifter, and doing so only requires a single pin. VRAM generally does not have two address buses, meaning that the CPU and graphics still have to interleave their accesses to the chip, but as a whole row of data is read out to the graphics driver, and that row might represent multiple scan lines on the screen, the number of times it has to interrupt the CPU can be greatly reduced.^[2]

Such operation is described in the paper "All points addressable raster display memory" by R. Matick, D. Ling, S. Gupta, and F. Dill, IBM Journal of R&D, Vol 28, No. 4, July 1984, pp. 379–393. To use the video port, the controller first uses the DRAM port to select the row of the memory array that is to be displayed. The VRAM then copies that entire row to an internal row-buffer which is a shift register. The controller can then continue to use the DRAM port for drawing objects on the display. Meanwhile, the controller feeds a clock called the shift clock (SCLK) to the VRAM's video port. Each SCLK pulse causes the VRAM to deliver the next data bit, in strict address order, from the shift register to the video port. For simplicity, the graphics adapter is usually designed so that the contents of a row, and therefore the contents of the shift-register, corresponds to a complete horizontal line on the display.

Through the 1990s, many graphic subsystems used VRAM, with the number of megabits touted as a selling point. In the late 1990s, synchronous DRAM technologies gradually became affordable, dense, and fast enough to displace VRAM, even though it is only single-ported and more overhead is required. Nevertheless, many of the VRAM concepts of internal, on-chip buffering and organization have been used and improved in modern graphics adapters.

• Video random-access memory