This article is rated Start-class on Wikipedia's content assessment scale. It is of interest to the following WikiProjects:

Computing Low‑importance This article is within the scope of WikiProject Computing, a collaborative effort to improve the coverage of computers, computing, and information technology on Wikipedia. If you would like to participate, please visit the project page, where you can join the discussion and see a list of open tasks.ComputingWikipedia:WikiProject ComputingTemplate:WikiProject ComputingComputing Low This article has been rated as Low-importance on the project's importance scale. This article is supported by Computer hardware task force (assessed as Low-importance).

The links to "dataspaces" and "hiperspaces" can't be corrected so I removed them. If anyone wants to create appropriate pages feel free (and restore the links). Martin Packer (talk) 20:44, 19 May 2013 (UTC)[reply]

It would be nice to add a CPU register table for the Z architecture, similar to that shown for the S/370 and various other mainframe, mini, and microprocessor CPUs. — Loadmaster (talk) 17:49, 8 November 2016 (UTC)[reply]

The term byte-accessible, which had been used in the article now here as ==IBM mainframe expanded storage==
is not telling the whole story.
http://stackoverflow.com/questions/4504775/endianness-inside-cpu-registers
refers to a situation described as:

"That's byte accessible, not byte "addressable'"

(loading a word into a pair of registers and then accessing one byte in one of the registers)
The IBM addressing system has an ADDRESS for each byte!

Not a deciding vote, but... Dr. Google prefers byte-addressable to byte-accessible Pi314m (talk) 17:44, 25 January 2017 (UTC)[reply]

I'm puzzled by the statement that both MVPG and MVCL are atomic. I think MVCL has always been interruptible (from GA22-7000-10 for S/370, SA22-7832-00 for Z/Architecture; note 8 on MVCL in both references describes some bad scenarios), and therefore can be observed as partially complete even on a single CPU. MVPG is not interruptible, but the last paragraph of its description in SA32-7832-00 implies that it can be observed as partially executed by other CPUs and channel programs: "not necessarily performed in a left-to-right direction as observed by other CPUs and by channel programs." Clem Dickey (talk) 18:03, 17 October 2017 (UTC)[reply]

Per above reference to 370 POP Note 8 (on p. 7-27 of GA22-7000-10), and after reviewing the Patent notes I cited in Z/Architecture, which highlights Dr. Google's disagreement with saying "Atomicity," it seems that using the diplomatic plural rather than "THE" to edit and mend/emend/amend non-compliance with:

• (From Greek "atomos", indivisible) Indivisible; cannot be split up (atomic from FOLDOC)
• a guarantee of isolation from interrupts, signals, concurrent processes and threads. (2nd sentence, Atomicity (programming), which redirects to Linearizability)
• an operation: guaranteed to complete either fully or not at all while waiting in a pause, and running synchronously when called by multiple asynchronous threads. (wiktionary: atomic, for computing)

to read:

These instructions do not comply with definitions for Atomic / AtomicAtomicity, although they can be used as a single instruction within documented timing and non-overlap restrictions.^[1]{{rp|Note 8, page 7-27}}<ref>"things are done immediately, and there is no chance of the instruction being half-completed or of another being interspersed. Used especially to convey that an operation cannot be interrupted." {{cite web |url=http://wwww.foldoc.org/atomic |title=Atomic from FOLDOC}}</ref>

is a good idea. I will also add as "Further Reading" Preshing on Programming - Atomic vs. Non-Atomic Operations (http://preshing.com/20130618/atomic-vs-non-atomic-operations) and another item.

My WP:OR on the matter is:

Atomicity is only from a limited perspective, since an external probe operating at a higher speed can observe a before/early-stage_during/mid-stage_during/late-stage_during/after of an event that the processor under observation, to the extent that it has a say, says is atomic. MVCL, according to the Principles of Operation manual, does not allow the operands to overlap, hence "not necessarily performed in a left-to-right direction as observed by other CPUs and by channel programs" is not only permitted but often a good way to do things, especially compared to MVC-loops of decades past. Pi314m (talk) 19:05, 18 October 2017 (UTC)[reply]

while s/390x redirects here, it is nowhere explained. s/390x and s/390 are two similar, but different things, this needs to be explained... --151.37.183.184 (talk) 17:57, 22 October 2018 (UTC)[reply]

"s/390x" doesn't exist. s390x now redirects to Linux on IBM Z § Hardware, which mentions the Linuxisms "s390" and "s390x". Guy Harris (talk) 22:45, 22 April 2023 (UTC)[reply]

I'm slowly hacking away at fleshing out the articles, and one of the issues is where to put the narrative and diagrams for the PSW. The options are:

• Put PSW in a stand-alone section
• Put PSW directly under Architectural details
• Put PSW under Registers
• Put the PSW in the same table as the other registers
• Put the PSW in a table containing only long and short PSW

In addition to suggestions on how to handle the PSW, I'd appreciate any feedback on overall organization of the article And,of course, I'd apprciate anybody willing to do some of the writing. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 19:16, 26 June 2024 (UTC)[reply]

Put it in the same table as the other registers, the same way it's done in IBM System/360 architecture, IBM System/370, IBM System/370-XA, and IBM Enterprise Systems Architecture. IBM System/370 shows both the BC and EC mode PSWs; this could probably do the same. Guy Harris (talk) 22:29, 26 June 2024 (UTC)[reply]

OK. What about the narrative for the PSW and FPC register? -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 09:00, 27 June 2024 (UTC)[reply]

PSW: z/Architecture should mention both long and short formats (and show them in the table), and describe the changes.

FPC: the bulk of the narrative belongs in ESA/390, as it was (as I guessed, given that most other ISAs equivalent contain a bunch of control and status bits that deal with IEEE 754) introduced with the binary floating-point feature. That section of IBM Enterprise Systems Architecture should have a description of the new floating-point capabilities that showed up with the G5 processor - new registers (even for hex floating-point) and IEEE 754 support. z/Architecture should mention the further changes to that register - and the rest of the changes for decimal floating-point arithmetic. Guy Harris (talk) 10:28, 27 June 2024 (UTC)[reply]

I'd say that should be mentioned in ESA/390, along with finally increasing the number of FP registers to 16, as it was introduced there, not in z/Architecture. Guy Harris (talk) 20:54, 26 June 2024 (UTC)[reply]

Done. Guy Harris (talk) 19:46, 30 June 2024 (UTC)[reply]

What architectural details should pages other than IBM System/360 architecture show? Changed or new details, or all, including stuff inherited from the predecessor architecture? Guy Harris (talk) 20:56, 26 June 2024 (UTC)[reply]

I've added another register to the register table, and the subtable title is rendered with a short width. Can anybody spot what I did wrong in BEAR? Thanks. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 17:56, 30 June 2024 (UTC)[reply]

Not sure whether there's a simpler fix, but putting two 32-bit boxes, as is done for other 64-bit registers, seems to fix the problem. Guy Harris (talk) 19:45, 30 June 2024 (UTC)[reply]

The sections about registers say that "Each CPU" has the register or set of registers in question. Is it clear that a "CPU" doesn't mean "a big cabinet containing multiple multi-core and possibly multi-threaded microprocessors" but "a CPU core" or, given that some (most?) z/Architecture processors are multithreaded, "a hardware thread in a CPU core"? Guy Harris (talk) 17:44, 1 July 2024 (UTC)[reply]

I'm not sure of the best way to word things. Current models are virtual multiprocessors; when the multithreading feature is enabled; there are multiple CPUs in a core, sharing some circuitry. If the feature is not installed, or is disabled, then CPU is synonymous with core. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 19:38, 1 July 2024 (UTC)[reply]