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Added a reference to a (somewhat biased but otherwise comprehensive) review article but still needs some primary references, especially for SIMOX and wafer seeding techniques. I have left the "needs references" template in place until I can dig up some appropriate sources to supplement the rest of the article.

Since performance is a complex factor of transistor design, materials choice, and lithography node I have removed any direct comparison between clock speed or switching energy (sic?) between "SOI" and "non-SOI" devices (although you can dig up dozens of such comparisons in the literature). I have also tried to avoid diving into the AMD vs. Intel fray, although my general survey of the various tech sites suggests that the (non-SOI) Core 2 outperforms the SOI-based Opteron products by most benchmarks. Anyone know an objective way of saying this? Or maybe it doesn't need to be said. Irene Ringworm 05:02, 31 December 2006 (UTC)[reply]

Comparing Intel's non-SOI 65nm chip to AMD's SOI 90nm chip does indeed make Intel come out the winner, but of course this doesn't mean SOI makes chips slower - just that SOI isn't the only technology advance capable of influencing processor speed. With comparisons like this out, I'm not sure of how to describe the benefits of SOI without going into (inaccessible to the layman) technical details? Mike1024 (t/c) 00:32, 3 January 2007 (UTC)[reply]

I like how you phrased that. Probably not worth opening up the Intel vs. AMD can of worms. I think that what's written now conveys that SOI provides a potential advantage and already finds use in many high end devices but it's not the only arrow in the process engineer's quiver. I'll just leave it be. Irene Ringworm 04:07, 3 January 2007 (UTC)[reply]

The statement that "SOI [is] one of the cornerstone technologies of modern digital integrated circuit manufacturing" just plain isn't true. From what I can gather poking around the internet, AMD uses SOI substrates in a small number of high performance processors and that Intel doesn't market any chips built on SOI. I will remove this in a future edit. Irene Ringworm 17:50, 27 December 2006 (UTC)[reply]

I agree that the statement isn't true. However, it's worth noting that IBM uses SOI for the Cell microprocessors used in gaming systems. Katherine Derbyshire

I caught the IBM Cell usage in my edit. Irene Ringworm 04:19, 3 January 2007 (UTC)[reply]

According to Soitec (admittedly not exactly an unbiased source) their SOI is in "high production" by ST, Freescale, IBM, AMD, Philips and Sony. This article also makes out that SOI is an increasingly common technology (Although some no-name news websites do tend to just reprint press releases with ads alongside). Of course, Intel doesn't feel the same way, making it hard to generalise about the entire high-end of the chip industry. Mike1024 (t/c) 00:15, 3 January 2007 (UTC)[reply]

SOITEC seems to be pretty good at non-standard marketing. The J. App. Phys. "focused review" article that I cited reads like an SOITEC press release in an ostensibly peer reviewed journal. Basically : here's a million ways for manufacturing SOI and here's why ours is the only one that will work. I've tried to take the NPOV road : SOI is used extensively but has not been universally adopted. We'll have to wait until Intel ships 45 nm to see if they're jumping on the SOI bandwagon. Irene Ringworm 04:19, 3 January 2007 (UTC)[reply]

One of my professors is (apparently) something of a leading light in this area, and the impression he gives me is that SOITEC's process is just plain good - that is, their process produces better results than other competing processes. Apparently SIMOX produces many more lattice defects because oxygen atoms are much larger than the hydrogen atoms smartcut uses. Unfortunately a lot of technical stuff in this industry is either kept secret by the company that comes up with it, and/or isn't very well described in books because the technology is so new and constantly changing. Mike1024 (t/c) 12:49, 4 January 2007 (UTC)[reply]

Clearly SOITEC has the upper hand in the industry as they appear to be supplying every major player producing SOI-based products. Their process is ingenious and precise. That being said, any sort of wafer bonding process is quite expensive because you chew up two conventional substrates to create a single SOI substrate. SIMOX, on the other hand, uses a single substrate and requires no specialized equipment not found in conventional manufacturing. Certainly the damage from the O implantation is a concern, but the oxide-forming anneal can be used to minimize its impact. SOITEC's process appears to be king at this point but the practical problems with competing technologies do not appear to be insoluble. Irene Ringworm 18:57, 4 January 2007 (UTC)[reply]

At this point, though, the infrastructure/economics of scale advantages of Soitec's process will be difficult to overcome. IBM evaluated SIMOX pretty recently, and found it lacking, which translates into a lack of funding for further improvements. Meanwhile, Soitec claims they can reuse the "handle" wafer, which is a big help for costs. Katherine Derbyshire

Re: "This process reduces the amount of electrical charge that the transistor has to move during a switching operation, increasing speed (up to 15%) and reducing switching energy (up to 30%) over CMOS-based chips."

Where do these 15% and 30% numbers come from? Needs a primary reference. Irene Ringworm 04:10, 27 December 2006 (UTC)[reply]

I'm not sure what the previous poster means by "alot of irrelevant things."

The only irrelevant part is the last line (completely inaccurate) about Intel using "high-k" and SOI. 1. You can't change the permittivity of silicon (or at least you don't in this situation...) 2. "High-K" refers to the gate dielectric, and not the substrate 3. In a high-k design, you put silicon dioxide on the silicon, then hafnium oxide or some other "high-k " dielectric on top of that 12.216.43.93 16:35, 6 December 2006 (UTC)[reply]

Removed the part about Intel using SOI along with high-k. The only work from Intel on SOI is their so-called depleted substrate transistor published in 2001.

Strictly speaking there is no limit on the silicon or oxide thickness. SOI transistors with silicon thickness as low as 2 nm have been demonstrated. Although buried oxide thickness is usually 50 nm or higher, there are proposals to use thinner oxides to use back gate to control the threshold voltage.

I'm a little surprised this page doesn't mention the advantages of SOI as regards CMOS latch up resistance. I don't suppose there's a whole lot to be said, but I think it's at least noteworthy. I would add the information myself, but I'm really not a silicon person. -- mattb @ 2007-02-10T23:48Z

the current first paragraph reads:

"The choice of insulator depends largely on intended application, with sapphire13vfur3jgrgbrgrgbrgjrbfdugcrcbrfefgfkalin www.het what ud oin .com being used for radiation-sensitive applications and silicon oxide preferred for improved performance and...."

Can someone fix this.... I dont know if I can. —Preceding unsigned comment added by 24.4.218.132 (talk) 06:29, 14 February 2008 (UTC)[reply]

Thanks.

ZenMasterThis (talk) 21:17, 10 June 2009 (UTC)ZenMasterThis[reply]

I am proposing that the contents of SOI MOSFET should be merged into this main article, as they both signify the same device. Duplicacy of content may be an issue.--Deepon (talk) 03:43, 28 October 2012 (UTC)[reply]

This section uses words such as obviously, as well as needs general copyediting. It may also include too much technical language. lv_oz2 (User page) (Talk page) 10:54, 3 August 2023 (UTC)[reply]

As of 2015 Intel was selling 14nm processors and 10nm is current technology for AMD. Saying 45nm is current technology should be corrected. 2600:100F:A020:F420:E8D3:194F:55B:4A2D (talk) 05:32, 2 July 2024 (UTC)[reply]