:''A [[Latch (hardware)|latch]] is a type of [[door]] or [[window]] [[lock (device)]]. A latching relay is a [[relay]] with two stable positions. In [[breastfeeding]], 'latch' refers to the baby's orientation with respect to the woman feeding it.

A '''latch''' is an [[electronics|electronic]] [[electrical network|circuit]] used to store information in [[asynchronous logic|asynchronous]] [[sequential logic]] systems. One latch can store one [[bit]] of information. Latches often occur in multiples, some of which have special names, such as the 'quad latch' (which can store four bits) and the 'octal latch' (eight bits). Latches are devices which have no clock input and change output state only in response to data input, while [[Flip-flop_(electronics)|flip-flop]]s have data inputs but change output state only in response to a clock input.

== SR latch ==

[[image:SR-NOR-latch.png|thumb|right|SR latch]]The logically simplest latch is the SR latch, where S and R stand for 'set' and 'reset'. The latch is constructed from a pair of cross-coupled [[NOR gate|NOR]] (negative [[OR gate|OR]]) [[logic gate]]s. The stored bit is present on the output marked Q.

Normally, in storage mode, the S and R inputs are both low, and [[feedback]] maintains the Q and <span style="text-decoration:overline">Q</span> outputs in a constant state, with <span style="text-decoration:overline">Q</span> the complement of Q. If S (set) is pulsed high while R is held low, then the Q output is forced high, and stays high when S returns low. On the other hand, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns low. If S and R are brought high at the same time, both NOR gates will output zeros, leading to the inconsistent output Q = !Q, so this condition must be avoided.

<table>

<tr><td>

{| class="wikitable" style="text-align:center"

! colspan="5"|SR latch truth table

|-

!S!!R!!Q!!Q_next!!Comment

|-

|0||0||0||0||Maintain

|-

|0||0||1||1||Maintain

|-

|0||1||0||0||Reset

|-

|0||1||1||0||Reset

|-

|1||0||0||1||Set

|-

|1||0||1||1||Set

|-

|1||1||0||0||Not allowed

|-

|1||1||1||0||Not allowed

|}

</td>

<td>&nbsp;</td>

<td>

{| class="wikitable" style="text-align:center"

! colspan="5"|SR small latch truth table

|-

!S!!R!!Q_n+1!! Comment

|-

|0||0||Q_n|| Maintain

|-

|0||1||0|| Reset

|-

|1||0||1|| Set

|-

|1||1||0|| Not allowed

|}

</td></tr></table>

== Inverted SR latch ==

[[image:sr-latch.png|thumb|right|<span style="text-decoration:overline">S</span>&nbsp;<span style="text-decoration:overline">R</span> latch]]Another simple latch is the <span style="text-decoration:overline">S</span><span style="text-decoration:overline">R</span> latch, where <span style="text-decoration:overline">S</span> and <span style="text-decoration:overline">R</span> stand for 'not set' and 'not reset'. This is constructed from a pair of cross-coupled [[NAND gate|NAND]] (negative [[AND gate|AND]]) [[logic gate]]s. NAND gates tend to be more compact than NOR gates in integrated circuits, so this variety is more common, despite the notational inconvenience of its active-low inputs.

Operation is similar to that of the SR latch, except that the <span style="text-decoration:overline">S</span> and <span style="text-decoration:overline">R</span> inputs are now active-low instead of active-high.

{| class="wikitable"

! colspan="7"|<span style="text-decoration:overline">S</span><span style="text-decoration:overline">R</span> latch truth table

|-

!S!!R!!<span style="text-decoration:overline">S</span>!!<span style="text-decoration:overline">R</span>!!Q!!Q_next!!Comment

|-

|0||0||1||1||0||0||Maintain

|-

|0||0||1||1||1||1||Maintain

|-

|0||1||1||0||0||0||Reset

|-

|0||1||1||0||1||0||Reset

|-

|1||0||0||1||0||1||Set

|-

|1||0||0||1||1||1||Set

|-

|1||1||0||0||0||-||Not allowed

|-

|1||1||0||0||1||-||Not allowed

|}

== Gated D Latch ==

A gated D latch is a latch constructed from an SR latch, two additional AND gates, a NOT gate, and two inputs, data (<math>D</math>) and gate (<math>G</math>). The S input is set to D AND G, while the R input is set to <span style="text-decoration:overline">D</span> AND G. When G is set to low (0), output does not change (in other words, Q_next equals Q). When G is set to high (1), output (Q) is equal to D.

<table class="wikitable">

<tr><td colspan = 5>'''Gated D latch truth table'''</td></tr>

<tr><td>'''G'''</td><td>'''D'''</td><td>'''Q'''</td><td>'''Q_next'''</td><td>'''Comment'''</td></tr>

<tr><td>0</td><td>0</td><td>0</td><td>0</td><td>No change</td></tr>

<tr><td>0</td><td>0</td><td>1</td><td>1</td><td>No change</td></tr>

<tr><td>0</td><td>1</td><td>0</td><td>0</td><td>No change</td></tr>

<tr><td>0</td><td>1</td><td>1</td><td>1</td><td>No change</td></tr>

<tr><td>1</td><td>0</td><td>0</td><td>0</td><td>Set data</td></tr>

<tr><td>1</td><td>0</td><td>1</td><td>0</td><td>Set data</td></tr>

<tr><td>1</td><td>1</td><td>0</td><td>1</td><td>Set data</td></tr>

<tr><td>1</td><td>1</td><td>1</td><td>1</td><td>Set data</td></tr>

</table>

==See also==

*[[Flip-flop (electronics)|Flip-flop]]

*[[Transparent latch]]

[[Category:Digital circuits]]

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