SPARC T5

Oracle SPARC T5
General information
Launched	2013
Discontinued	2017
Performance
Max. CPU clock rate	3.6 GHz
Cache
L1 cache	16×(16+16) KB
L2 cache	16×128 KB
L3 cache	8 MB
Architecture and classification
Technology node	28 nm
Instruction set	SPARC V9
Physical specifications
Cores	16
Products, models, variants
Core name	S3
History
Predecessor	SPARC T4
Successor	SPARC M7

SPARC T5 is the fifth generation multicore microprocessor of Oracle's SPARC T series family.^[1] It was first presented at Hot Chips 24 in August 2012,^[2] and was officially introduced with the Oracle SPARC T5 servers in March 2013.^[3] The processor is designed to offer high multithreaded performance (16 cores per chip, with 8 threads per core), as well as high single threaded performance from the same chip.^[4]

The processor uses the same SPARC S3 core design as its predecessor, the SPARC T4 processor, but is implemented in a 28 nm process and runs at 3.6 GHz.^[5] The S3 core is a dual-issue core that uses dynamic threading and out-of-order execution,^[6] incorporates one floating point unit, one dedicated cryptographic unit per core.^[7]

The 64-bit SPARC Version 9 based processor has 16 cores supporting up to 128 threads per processor, and scales up to 1,024 threads in an 8 socket system.^[4] Other changes include the support of PCIe version 3.0 and a new cache coherence protocol.^[5]

This chart shows some differences between the T5 and T4 processor chips.

The SPARC T5 also introduces a new power management feature that consists of hardware support in the processor, and the software that allows system administrator to use the feature. Users select the policy how the system responds to over-temperature and over-current events. The dynamic voltage and frequency scaling (aka DVFS) policy can be set to maintain peak frequency, or to trade off between performance and power consumption.^[5]

The SPARC T5 processor is used in Oracle's entry and mid-size SPARC T5-2, T5-4, and T5-8 servers. All servers use the same processor frequency, number of cores per chip and cache configuration.^[12]

The T5 processor includes a crossbar network that connects the 16 cores with the L2 caches to the shared L3 cache. Multiprocessor cache coherence is maintained using a directory-based protocol.^[5] The design scales up to eight sockets without additional silicon (glueless). The snooping based protocol used in SPARC T4 systems was replaced in order to reduce memory latency and reduce coherency bandwidth consumption.^[5][13]