In the design of modern computers, memory geometry describes the internal structure of random-access memory. Memory geometry is of concern to consumers upgrading their computers, since older memory controllers may not be compatible with later products. Memory geometry terminology can be confusing because of the number of overlapping terms.

The geometry of a memory system can be thought of as a multi-dimensional array. Each dimension has its own characteristics and physical realization. For example, the number of data pins on a memory module is one dimension.

Memory geometry describes the logical configuration of a RAM module, but consumers will always find it easiest to grasp the physical configuration. Much of the confusion surrounding memory geometry occurs when the physical configuration obfuscates the logical configuration. The first defining feature of RAM is form factor. RAM modules can be in compact SO-DIMM form for space constrained applications like laptops, printers, embedded computers, and small form factor computers, and in DIMM format, which is used in most desktops.^{[citation needed]}

The other physical characteristics, determined by physical examination, are the number of memory chips, and whether both sides of the memory "stick" are populated. Modules with the number of RAM chips equal to some power of two do not support memory error detection or correction. If there are extra RAM chips (between powers of two), these are used for ECC.

RAM modules are 'keyed' by indentations on the sides, and along the bottom of the module. This designates the technology, and classification of the modules, for instance whether it is DDR2, or DDR3, and whether it is suitable for desktops, or for servers. Keying was designed to make it difficult to install incorrect modules in a system (but there are more requirements than are embodied in keys). It is important to make sure that the keying of the module matches the key of the slot it is intended to occupy.^{[citation needed]}

Additional, non-memory chips on the module may be an indication that it was designed^{[by whom?]} for high capacity memory systems for servers, and that the module may be incompatible with mass-market systems.^{[citation needed]}

As the next section of this article will cover the logical architecture, which covers the logical structure spanning every populated slot in a system, the physical features of the slots themselves become important. By consulting the documentation of your motherboard, or reading the labels on the board itself, you can determine the underlying logical structure of the slots. When there is more than one slot, they are numbered, and when there is more than one channel, the different slots are separated in that way as well – usually color-coded.^{[citation needed]}

In the 1990s, computers using cache-coherent non-uniform memory access were released, which allowed combining multiple computers that each had their own memory controller such that the software running on them could use I/O devices, memory, and CPU of all participating systems as if they were one unit (single system image). With AMD's release of the Opteron, which integrated the memory controller into the CPU, NUMA systems that share more than one memory controller in a single system have become common in applications that require the power of more than the common desktop.^{[citation needed]}

Channels are the highest-level structure at the local memory controller level. Modern computers can have two, three or even more channels. It is usually important that, for each module in any one channel, there is a logically identical module in the same location on each of the other populated channels.^{[citation needed]}

Module capacity is the aggregate space in a module measured in bytes, or – more generally – in words. Module capacity is equal to the product of the number of ranks and the rank density, and where the rank density is the product of rank depth and rank width.^[1] The standard format for expressing this specification is (rank depth) Mbit × (rank width) × (number of ranks).^{[citation needed]}

Ranks are sub-units of a memory module that share the same address and data buses and are selected by chip select (CS) in low-level addressing. For example, a memory module with 8 chips on each side, with each chip having an 8-bit-wide data bus, would have one rank for each side for a total of 2 ranks, if we define a rank to be 64 bits wide. A module composed of Micron Technology MT47H128M16 chips with the organization 128 Mib × 16, meaning 128 Mi memory depth and 16-bit-wide data bus per chip; if the module has 8 of these chips on each side of the board, there would be a total of 16 chips × 16-bit-wide data = 256 total bits width of data. For a 64-bit-wide memory data interface, this equates to having 4 ranks, where each rank can be selected by a 2-bit chip select signal. Memory controllers such as the Intel 945 Chipset list the configurations they support: "256-Mib, 512-Mib, and 1-Gib DDR2 technologies for ×8 and ×16 devices", "four ranks for all DDR2 devices up to 512-Mibit density", "eight ranks for 1-Gibit DDR2 devices". As an example, take an i945 memory controller with four Kingston KHX6400D2/1G memory modules, where each module has a capacity of 1 GiB.^[2] Kingston describes each module as composed of 16 "64M×8-bit" chips with each chip having an 8-bit-wide data bus. 16 × 8 equals 128, therefore, each module has two ranks of 64 bits each. So, from the MCH point of view there are four 1 GB modules. At a higher logical level, the MCH also sees two channels, each with four ranks.

In contrast, banks, while similar from a logical perspective to ranks, are implemented quite differently in physical hardware. Banks are sub-units inside a single memory chip, while ranks are sub-units composed of a subset of the chips on a module. Similar to chip select, banks are selected by bank select bits, which are part of the memory interface.^{[citation needed]}

The lowest form of organization covered by memory geometry, sometimes called "memory device". These are the component ICs that make up each module, or module of RAM. The most important measurement of a chip is its density, measured in bits. Because memory bus width is usually larger than the number of chips, most chips are designed to have width, meaning that they are divided into equal parts internally, and when one address "depth" is called up, instead of returning just one value, more than one value is returned. In addition to the depth, a second addressing dimension has been added at the chip level, banks. Banks allow one bank to be available, while another bank is unavailable because it is refreshing.^{[citation needed]}

Some measurements of modules are size, width, speed, and latency. A memory module consists of a multiple of the memory chips to equal the desired module width. So a 32-bit SIMM module could be composed of four 8-bit wide (×8) chips. As noted in the memory channel part, one physical module can be made up of one or more logical ranks. If that 32-bit SIMM were composed of eight 8-bit chips the SIMM would have two ranks.^{[citation needed]}

A memory channel is made up of ranks. Physically a memory channel with just one memory module might present itself as having one or more logical ranks.^{[citation needed]}

This is the highest level. A typical computer has only a single memory controller with only one or two channels. The logical features section described NUMA configurations, which can take the form of a network of memory controllers. For example, each socket of a two-socket AMD K8 can have a two-channel memory controller, giving the system a total of four memory channels.

Various methods of specifying memory geometry can be encountered, giving different types of information.

(memory depth) × (memory width)

The memory width specifies the data width of the memory module interface in bits. For example, 64 would indicate a 64-bit data width, as is found on non-ECC DIMMs common in SDR and DDR1–4 families of RAM. A memory of width of 72 would indicate an ECC module, with 8 extra bits in the data width for the error-correcting code syndrome. (The ECC syndrome allows single-bit errors to be corrected). The memory depth is the total memory capacity in bits divided by the non-parity memory width. Sometimes the memory depth is indicated in units of Meg (2²⁰), as in 32×64 or 64×64, indicating 32 Mi depth and 64 Mi depth respectively.

(memory density)

This is the total memory capacity of the chip. Example: 128 Mib.

(memory depth) × (memory width)

Memory depth is the memory density divided by memory width. Example: for a memory chip with 128 Mib capacity and 8-bit wide data bus, it can be specified as: 16 Meg × 8. Sometimes the "Mi" is dropped, as in 16×8.

(memory depth per bank) × (memory width) × (number of banks)

Example: a chip with the same capacity and memory width as above but constructed with 4 banks would be specified as 4 Mi × 8 × 4.

• DIMM
• List of device bandwidths
• Dynamic random access memory
• Random-access memory
• Memory organisation
• Memory address
• Memory bank
• Bank switching
• Double-sided RAM
• Dual-channel architecture
• Page address register

• "RAM", Mainboard (FAQ), IXT labs, 2006.
• FAQ, RAMpedia, archived from the original on 2010-05-16.
• "Part 1", RAM guide, Ars technica.
• "Banks", RAM, PC guide.
• KHX6400D2 1G (PDF) (data sheet), Value RAM, archived from the original (PDF) on 2012-03-10, retrieved 2010-08-05.
• 307502 (PDF) (data sheet), Intel.